1. Field of the Invention
The present invention relates to micro-controller integrated circuits including a customizable logic area and a predefined logic area that are accessible via the microprocessor. More particularly, the present invention relates to architecture to make connections between the customizable area and the predefined logic areas.
2. The Prior Art
Due to the wide variety of available software applications, it is difficult to design a standard microcontroller product that includes all possible modules to efficiently address these applications. The application specific integrated circuit (ASIC) market addresses that need by allowing a user to specify custom modules. The initial development cost of an ASIC remains expensive. A known work-around consists of adding a customizable area of logic to an already predefined microcontroller logic, the customizable area being formed as a field programmable gate array or other logic that can be customized by, for example, modifying the metal interconnect layers. This last solution is a trade-off between the size of the logic, which is smaller than FPGA area for an equivalent function, and a front-end cost including the design of the metal layer, and one time customization cost.
In such a prior-art architecture, the predefined logic implements a microcontroller function that cannot be modified but contains access points that connect to the customizable logic area. These access points are generally the system bus of the microcontroller.
Referring now to FIG. 1, an illustrative prior-art architecture of this type is shown. A basic micro-controller architecture 10 including a customizable logic module includes the microprocessor 12 that executes a set of instructions that can be stored outside the integrated circuit in a memory device (not shown) which is controlled by the external bus interface (EBI) 14 that communicates with the external memory via EBI bus portions 16 and 18 as is known in the art. The set of instructions may also be located in a ROM or Embedded Flash acting as an on-chip memory 20. An address decoder module 22 selects one module from among all possible modules coupled to a system bus 24 over select lines 26, 28, 30, or 32 as is known in the art. The system bus 34 includes (not shown) an address bus, a write data bus, a read data bus and control signals such as read/write. Among the modules commonly encountered in such a system are an interrupt controller 36 and a UART 38 that sends and receives signals via I/O 40. A customizable area 42 may be included to allow a user to implement a custom function in the system. Customizable area 42 may send and receive signals via I/O 44. Clock terminal 46 supplies a clock signal to time all the modules and reset terminal 48 supplies a reset signal to initialize all the modules.
The microprocessor 12 executes instructions that can be stored outside the chip by driving the address bus 34 to a value corresponding to the EBI module 14. The address decoder 22 asserts the corresponding selection signal 26. To fetch the instruction, the direction control (read/write) signal of the system bus is asserted for read operation mode. The value can be either logical 1 or 0 depending on the system bus protocol. The EBI module 14 then drives the external memory device to obtain the data required by the microprocessor 12. EBI bus portion 16 is driven by the EBI module 14, and by the address and control signal set. The off-chip memory returns the instruction to be executed on EBI bus portion 18. The EBI module returns the instruction data value on internal system bus 34 and the microprocessor 12 is then ready to execute the instruction.
If the instruction is a write instruction to one of the modules coupled to the system bus 34, the microprocessor 12 performs another similar fetch to obtain the destination address of the peripheral device to which the data must be written. The microprocessor 12 then executes the write instruction to the selected peripheral by asserting on the system address bus a value selecting (for example) the UART module 38. The address decoder 22 deselects the EBI 14 by clearing the associated selection signal 32 and asserts the selection signal 28 corresponding to the UART module 38.
Being selected for a write operation, the UART module 38 writes into its internal registers the value on the write data bus portion of system bus 34. The other modules receive this value but do not take any action because they are not selected. The UART module 38 converts the parallel internal stored data to a bit stream that is clocked out on I/O 40.
The instructions are sequentially executed and perform read or write operations on the system bus. The microprocessor 12 can also be triggered by a peripheral using the interrupt line 50 driven by the interrupt controller 36, which handles the priorities of the interrupt lines 52 and 54 coming from peripheral modules 38 and 42. For example if the expected result from a peripheral is known to have a latency of several tens of clock cycle, it is better to trigger the interrupt line rather than wait for the result by executing some kind of no-operation instruction, especially when several peripherals, such as UARTs and crypto-processors, have a long latency response compared to the clock cycle period.
The customizable logic area 42 can be designed using an FPGA-based architecture. Therefore this logic will be able to be programmed in the field. The architecture can also be gate-array based. In this case, for the same area, the cell density is much more higher than in an FPGA, but the functionality can be defined only once. To obtain the desired function, the metal layers must be designed according to the cells (gates) available on the gate array. In the gate array, the placement of the gates is always the same whatever the functionality.
As a consequence, it is cheaper to design a new micro-controller with this method rather than by generating a full masks reticle for each new circuit. Only the last layers are redesigned and manufacture time is significantly reduced.
The customizable logic area 42 needs to be connected to predefined logic to be accessible by the microprocessor 12. Therefore, the system bus 34 communicates with customizable logic 42. For example, if the system bus 34 selects data using non-tristate cells (i.e. multiplexers using NAND or other gates), these multiplexers will have dedicated inputs that will be driven by circuitry in the customizable logic area 42. To read data from the customizable logic, the multiplexers located in the predefined logic must have dedicated inputs to receive data from the customizable logic. When a circuit is embedded in the customizable area, it is likely that read access to this circuit will be needed. In such a case, the dedicated inputs of the predefined logic multiplexers will be driven by the customized circuitry. But it is also possible to employ a circuit that requires only write access. In this case it is mandatory for an architecture such as shown in FIG. 1 or a similar architecture to tie the dedicated inputs of predefined logic multiplexers to a known logical value (GROUND or VDD) to avoid CMOS floating inputs as is known in the art. This can be done, of course, only in the customizable area to avoid the need to modify the layout of the predefined logic.
To address as many applications as possible, several sources of interrupt are taken into account in the customizable area. Three sources are shown in FIG. 1. If the customer has a module using a single interrupt source, the two remaining interrupt lines must be tied to ground to render them inactive. Again this must be done in the customizable area to avoid the need to modify the layout of the predefined logic.
The same idea applies for the address decoder 22. Several signals 30 from the address decoder 22 are already decoded and routed to the customizable logic area 42. This kind of routing is necessary to enable the microprocessor 12 to gain access to the customizable logic area 42.
Due to increasing requests on embedded security features including, but not limited to protect privacy, to keep the firmware from being copied, there is a need to protect information that is being processed by the circuit. The data that are internally processed are difficult to analyze because it is difficult to gain internal access using non-intrusive methods, and therefore may be more difficult to be copied. But when an external bus interface 14 exists to provide an interface to large off-chip memories, it may be very important to encrypt data prior to driving it onto the PAD buffers for I/O 16 and 18. The ciphering algorithm must be kept secret for each original equipment manufacturer to maintain the privacy of the intellectual property such as firmware or other embedded software.
This issue applies only to transfers between the microcontroller and off-chip memories (serial/parallel) and not for point to point communication links where data are ciphered to keep from being read while in transfer by a third party that may be connected on the same communication network. In such a case the ciphering algorithm is standard in order to provide the ability to communicate with any remote terminal. Individual keys must be known by both sender and recipient to perform correct data exchanges.